diff --git a/syntax/arm.vim b/syntax/arm.vim index 7e29611..de11318 100644 --- a/syntax/arm.vim +++ b/syntax/arm.vim @@ -18,7 +18,7 @@ if version >= 508 || !exists("did_armv6_syntax_inits") command -nargs=+ HiLink hi def link endif - so :p:h/include/arm_base_syntax.vim + so :p:h/include/armv6_base_syntax.vim HiLink armv4Instr armv6Instructions HiLink armv4Stack armv6Instructions @@ -37,6 +37,7 @@ if version >= 508 || !exists("did_armv6_syntax_inits") HiLink armv6STR armv6Instructions HiLink armv7Instr armv6Instructions + HiLink armVfpInstr armv6Instructions HiLink armNumericOp armOperator HiLink armRelative armOperator diff --git a/syntax/include/arm_base_syntax.vim b/syntax/include/arm_base_syntax.vim index 6e3091f..0a5933a 100644 --- a/syntax/include/arm_base_syntax.vim +++ b/syntax/include/arm_base_syntax.vim @@ -36,15 +36,6 @@ syn keyword armRegister R0 R1 R2 R3 R4 R5 R6 R7 R8 syn keyword armRegister R9 R10 R11 R12 R13 R14 R15 FP SP LR PC SPSR CPSR CPSR_c CPSR_cxsf BP syn keyword armRegister A1 A2 A3 A4 V1 V2 V3 V4 V5 V6 V7 V8 -" VFP/NEON registers -let i = 0 -while i < 32 - exe 'syn match armRegister "S' . i . '\>"' - exe 'syn match armRegister "D' . i . '\>"' - exe 'syn match armRegister "Q' . i . '\>"' - let i = i + 1 -endwhile - " Conditional field to avoid repetition let armCond = '\%(AL\|CC\|CS\|EQ\|GE\|GT\|HI\|HS\|LE\|LO\|LS\|LT\|MI\|NE\|PL\|VC\|VS\)\?' @@ -79,14 +70,5 @@ exec 'syn match armv5STR "\%(STR\)' . armCond . 'D\>"' HiLink armv4LDR armv5LDR HiLink armv4STR armv5STR -" -" ARMv6 instructions -" - - -" -" VFP/NEON -" - "syn match armRelative "@R[0-7]\|@a\s*+\s*dptr\|@[ab]" diff --git a/syntax/include/armv6_base_syntax.vim b/syntax/include/armv6_base_syntax.vim index af6d28f..52ff642 100644 --- a/syntax/include/armv6_base_syntax.vim +++ b/syntax/include/armv6_base_syntax.vim @@ -35,7 +35,7 @@ exec 'syn match armv7Instr "\%(DBG\|DMB\|DSB\|ISB\|SEV\|WFE\|WFI\|YIELD\)' . arm " " VFP/NEON " -exec 'syn match armVfp "\%(\)' . armCond . '\>"' +exec 'syn match armVfpInstr "\%(VMUL\|VNMUL\|VMLA\|VMLS\|VNMLS\|VNMLA\|VADD\|VSUB\|VDIV\|VABS\|VNEG\|VSQRT\|VCMPE\?\|VCVT[TB]\?\|VMOV\|VMSR\|VMRS\|VSTR\|VSTM\%(DB\|IA\|EA\|FD\)\?\|VPUSH\|VLDR\|VLDM\%(DB\|IA\|EA\|FD\)\?\|VPOP\)' . armCond . '\>"' syn match armVfp